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vco + noise + veriloga
Hi
I have simulated pss and pnoise of a VCO and have extracted a table of its phase noise vs frequency in dBc/Hz. Now I need to estimate how much jitter this contributes to a PLL loop. For this I have a PLL loop with ideal elements, but I want the ideal VCO block to take...
ocean script plotting waveform
How do I modify the above command given by dlevy212 to include 2 variables? I need this because I run corners over supply and temperature variations and I need the waveform's label to tell me which combination of the variables it corresponds to. I tried using all...
kcl violation asitic
Hi, has anyone met a problem of 'KCL violation' warning in ASITIC?
I used the simple sq command to create a square spiral inductor. but when analysing by pix command, this warning appears. Does it have any effect on the subsequent simulation results?
kcl violation
I too am getting the same warning but I cant figure out what is wrong. Im not sure if this warning has any effect on the simulation results. Does anyone have any idea?
dll transfer function
Hi all
I would like to know the loop gain of a typical charge pump DLL. Also, I have seen the gain term \[ K_{VCDL} \] being used often, but dont know its exact meaning. Does it depend on the number of delay stages in the DLL? And does \[K_{VCDL} \] have any upper and...
PLL's Filter Design
@Mouzid
There was an error in my previous message. To get a zero you need to have the charge pump driving a series combination of resistor and capacitor and not a parallel combination as I had mentioned.
pll filter design
First of all you need decide if you want to use an active or a passive filter. Lets say you design the simpler of the two which is a passive filter. Now you must decide on the bandwidth of your PLL (which is the frequency on the bode plot where the loop gain of the PLL crosses...
Re: Suggestions about inductorless VCOs above 3 MHz frequenc
@ee07d003
What do you mean by "noise gets added only after a few cycles"?
Added after 14 minutes:
@gunturikishore
You can make oscillator tank circuit similar to an LC tank using capacitor alone with transconductors connected in...
But in reality higher gain gives proportionally higher frequency.
This is because an amplifier with higher gain shows a steeper rise at its output than one with lower gain for the same input. This means that the succeeding inverting amplifier gets triggered much earlier than the amplifier with...
charge pump and pnoise
Hello people
I need to find the phase noise contributed by a phase/frequency detector + charge pump combination which are part of a frequency synthesizer. When the synthesizer is locked, both the inputs to the PFD are of the same frequency and hence the beat frequency...
Yes I guess real ring oscillators do eventually hit some swing saturation. But Im simulating with ideal amplifier stages and I'm unable to explain the direct dependence of frequency on the amplifier gain.
Well say I have some ideal amplifier whose gain I can change without varying its 3dB BW. In that case, as philipwang said, the frequency musn't vary. But
I read somewhere that the frequency is proportional to gain (assuming again BW is constant), and when I simulated this using the afore...
What happens to the frequency of oscillation of a ring oscillator if I increase the gain of each amplifier stage above the minimum required gain levels? Would the frequency increase or decrease? I would definitely prefer a time-domain explanation.
cml latch design
hi
you can use any common mode for clk provided the clk swing is capable of completely switching the mos on or off. i have designed latches in which the clk mos are either in triode or cut-off, but never in saturation. but i guess u need to have your input mos pair in...
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