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Recent content by nandithaa_m

  1. N

    FIFO Basics and Design

    Can anyone help find material for FIFO basics and design in verilog ? I am looking for some basic concepts of FIFO and its design. I am new to designs with Clock Domain Crossing and wanted to understand the implementation of FIFO in this context.
  2. N

    Scan Mechanism with Example

    couldnt find keyword for getting a perfect example ? Can you post a link ?
  3. N

    Scan Mechanism with Example

    Can anyone explain me scan mechanism with a simple example ?
  4. N

    Setup/Hold scenario when pos edge launch flipflop - neg edge capture flipflop

    Thanks for the responses.
  5. N

    Interview Question for ASIC Design

    Thanks for the responses. It helps.
  6. N

    Interview Question for ASIC Design

    Hi Guys, I am preparing for an interview and can you provide me an answer for the following question ? Why do designers avoid a clock with 0 rise time ?
  7. N

    Setup/Hold scenario when pos edge launch flipflop - neg edge capture flipflop

    Hi Guys, Thanks for the response. The hold violation case matches my assumptions. This is the equation that I have for setup. Looks like there is less chance of set-up in this scenario. I derived setup equation based on the schematic posted above...
  8. N

    Setup/Hold scenario when pos edge launch flipflop - neg edge capture flipflop

    Hi Guys, Thanks for the response. The hold violation case matches my assumptions. This is the equation that I have for setup. Looks like there is less chance of set-up in this scenario. I derived setup equation based on the schematic posted above...
  9. N

    Setup/Hold scenario when pos edge launch flipflop - neg edge capture flipflop

    Can anyone help me prove why there will not be any hold violations if launch ff is pos-edge and capture ff is neg-edge ? Also, can you help me understand setup scenario also ?
  10. N

    Help about Formality Tutorial

    Can you post DC Compiler Material you have ? Thanks in advance
  11. N

    Help needed in designing DAC ..

    I am trying to design a 3 bit DAC which should work at 10 MHz. I started designing by using R-2R ladder. I gave the inputs such that digital state changes from 000 to 111 for every 10 MHz. I am unable to get the exact output. If I slow down the clock its working (suppose to 1 MHz, 100k). Its...
  12. N

    input loading of an opamp..

    how to do s parameter analysis in multisim 10.0 i havent found anything like that..
  13. N

    input loading of an opamp..

    how to check input loading of an opamp (should be in picofarads)? (in the design question it was mentioned that it should be less than 0.12pf) i have no idea what to do..can you please help me.. thanks in advance
  14. N

    How to enhance the gain of an opamp?

    Opamp design can any body help please..just gimme a basic circuit..i will build it from there..its urgent..
  15. N

    How to enhance the gain of an opamp?

    how to enhance the gain of opamp?
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