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Hi everyone,
I am using fixed_pkg.vhd for our project. I want to divide two signals of type sfixed. When I use normal division ('/') operand I am able to simulate. But when I try to synthesize, it shows error division operand cannot be synthesize. Can anyone please let me know how to proceed. Is...
In my project i have two decoders which runs iteratively, each has same three modules in it. I want performance in terms of speed and hardware. Priority is for speed followed by hardware.
Among component instantiation and procedure, which will give me better performance.
Anyone who knows about...
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