Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I am not sure, what you are referring to as "sim lib", but let me know, whether the below explanation answers your query.
1. The gate-level netlist, along with the Verilog library files (obtained from foundry) are used as input to NCVerilog simulation.
2. The spice model files (obtained from...
I am a student, working on Digital IC design. When I used Nanosim for Post-Layout simulation, it generates a lot of state comparison errors.
The inputs to Nanosim are
1. hspiceD netlist generated from Cadence Virtuoso extracted view from Layout.
2. Vector file generated from VCD file (obtained...
Usually, the below method is followed.
Stream in the GDSII file generated from Encounter to Cadence.
Check for DRC and LVS and all the checks and simulations.
Stream out the Physical GDSII file from Cadence, which is submitted to foundry.
Hope, this helps.
We need to connect the drain and gate of NMOS to VDD, and view the output at source, as the drain of NMOS must be at a higher potential than source for its normal operation.
When the source potential reaches VDD-Vth, the gate-to-source voltage Vgs become Vth. Any further increase in source...
I had to change my net names in the vector file, and the supply and ground net names (from vdd and gnd to n42 and n41), as in the SPICE netlist. One I did that, the simulation went on without stalling.
I had to change the supply and ground net names (from vdd and gnd to n42 and n41), as in the SPICE netlist. One I did that, the simulation did not stall at DC Initialization.
Hi Keith,
Thanks for your reply. If had to change the library instead of the netlist, how should I go about it.
How should I add the "$SUB" parameter in the netlist to the library, in the below statement.
.SUBCKT RDIFFP3 D S W=1e-6 L=1e-6
regards,
saravanan
I am working on Nanosim Simulation with a hspiceD netlist generated from Cadence ADE. The simulation stalls at the step given below.
DC Initialization
Initializing level 0 ...
I added the following line to skip dc initialization in the *.cfg file. The initialization operation is postoned at...
Hi,
I am working on design simulation using Nanosim, and am facing this error below.
WARNING:NanoSim:0x202040aa:s is unused port in instance "xrx3/x12/r0" of subckt "rdiffp3".
The netlist used for Nanosim was obtained from Calibre PEX.
When I referred to the instance "xrx3/x12/r0" in the...
Yes. Now the error does not occur on that line after adding the Prefix "X" to it.
Why does this happen? How can I solve this problem?
regards,
saravanan
Thanks.
The lines 781, 782 and 783 are copied below.
rX7/X17/R2 N_AUDIO_IN[7]_X7/X17/R2_pos N_X7/X17/9_X7/X17/R2_neg RDIFFP3 w=3e-06
+ l=9.6e-06 $SUB=N_VDD!_X3/X12/R2_sub
dX7/X17/D3 N_GND!_X3/X12/M7_b N_X7/X17/9_X7/X17/D3_neg ND AREA=7.5 PJ=10.2284
I am assuming that the error it shows is...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
