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Recent content by nana_7488

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    Is SXCUT layer without label will effect the physical layout and IC functionality?

    Hi Thanks for the info. Just wondering is it still not affect my layout if I do put the SXCUT layer at my subc which connected to bulk of my NFET transistor? I did connected all the subc to the same ground, but is the SXCUT break the region of the substrate it's assume like my layout having...
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    Is SXCUT layer without label will effect the physical layout and IC functionality?

    Hi, I'm using IBM PDK cmrf8sf. Do you know anything about SXCUT in this?Thanks
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    Is SXCUT layer without label will effect the physical layout and IC functionality?

    Hi I've tried to look at the PDK, it only said that SXCUT layer is used to break the substrate region.No other information on the properties or effect, is it only for the tool or effect the actual physical layout. Thanks
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    Is SXCUT layer without label will effect the physical layout and IC functionality?

    Hi Hope to find some answer to my problem. I did put SXCUT layer in my layout but didn't label it using SXCUT net. I do have LVS error on soft substrate pin error. I know that SXCUT layer is use to generate isolated substrate region, but not associated with any mask layer, so what happen to my...
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    import GDS2 from Mentor Graphic to Cadence, the layer change

    Hi all I've got a problem when importing my gds2 file that I've created using IC Station in Mentor Graphics to Cadence. The metal layer were difference when I open it in Cadence eg M1 was change to K5 layer in cadence. Please somebody help me. Thanks
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    How to make an FPGA control in ASIC?

    Hi I'm try to test my full custom AES chip using FPGA (Virtex-5) with ML505 board from Xilinx. I want the FPGA to give the test vector input to the chip and display the output of my chip in LCD. Has anyone ever done like this before and give me some idea how to do it. Thanks
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    Netlist difference between LVS layout and schematic in Calibre

    I will have a look on this one.. Can you explain how to do it this way?what do you mean by always bring the sub! net to an explicit terminal? Thanks
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    Netlist difference between LVS layout and schematic in Calibre

    This is global device in image in the top level schematic. For each cell I've used subc device which is the property is subc, not Global like VDD and VSS. Each individual cell have a LVS clean, the LVS problem only happen when I've used it together to form a top level layout. I thought this...
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    Netlist difference between LVS layout and schematic in Calibre

    It is because for VDD and VSS I've used global VDD and VSS device from the library.but for the global sub! I've found one global device from the library and used it, because when I've checked the property it is global, just changed the value to sub!. I don't have other any idea how to make...
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    Netlist difference between LVS layout and schematic in Calibre

    That's confused me too, I don't know how it's happen. My schematic have sub! for each of the cell, not sub!_esc1. You see here, I think the global sub! I add is fine in the layout, but it cause badly to the schematic
  11. N

    Netlist difference between LVS layout and schematic in Calibre

    Hi I've put global sub! (which I thought the right global) in the schematic, but other error appeared. See the picture below I'm so stucked now...please help me..
  12. N

    Netlist difference between LVS layout and schematic in Calibre

    I'm using cmrf8sf V1.7.0.0DM, and based on the layer info, SXCUT_NET is for label purpose. How I'm gonna add global sub! in schematic, is it with the subc device?sorry if this like dumb question to you..i just want to make sure I'm done it right. Thanks
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    Netlist difference between LVS layout and schematic in Calibre

    so you suggest I add global sub! in top schematic?
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    Netlist difference between LVS layout and schematic in Calibre

    Hi When I add sub! label using SXCUT_NET (as no SXCUT:label in the tech), it happen to have error of missing port sub! in schematic with the 3 error that I've posted before, if I add using SXCUTPIN, the missing port error gone, but the rest of the error still there. Seem it didn't work. Any...
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    Netlist difference between LVS layout and schematic in Calibre

    Hi. I don't prefer to put global subc in top shematic Following are my schematic and netlist top layout Hope can solve it because I need to move on to other design. Thanks
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