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I am using video PHY core IP from xilinx for HDMI transmitter with kintex7 device. It has 3 gigabit transmitters.The phy core has code for TX Phase Alignment to Minimize the TX Lane-to-Lane Skew. But it seems that Tx phase alignment is not completing. I looked inside the phase alignment code and...
Dear TrickyDicky, dpaul,
I really appreciate you went through papers and gave your feedback.
Even I acknowledge that it is difficult to cover all the possible testbench scenarios.
So I thought if some script or tool is available, I can try to modify it and mature it.
Conclusion:
It is not good...
Hello dpaul,
Thanks a lot for reply.
The motivation to do is to speed up the verification of DUT(RTL design). I got 2-3 research papers people worked on the automation of this process
https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.99.639&rep=rep1&type=pdf...
Hello,
I have tested my DUT in simulation using VHDL test bench. The test bench has behavioral coding.
I want to use the same test bench for validation on FPGA. So the test bench needs to be synthesizable.
My query: Are there any other standard tools from vendors (like synopsys, cadence...)...
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