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Recent content by n.suresh60

  1. n.suresh60

    How to implement a chip level design.what measures need to take , and how to do it..?

    please any expert or known person share your knowledge on this question.. what are the measures need to consider to start implementation of Full chip design with hierarchical flow,like... *how to partition the design, *how to do time Budgeting, * how to do parallel top level sta, and block...
  2. n.suresh60

    [SOLVED] How to fix Fanout violations after postRoute?

    I'm using Soc Encounter for implementation....
  3. n.suresh60

    [SOLVED] How to fix Fanout violations after postRoute?

    Hi frinds.. after post Route fixing setup/hold still i'm seeing some transition violation and fanout violations how to fix them , what are the violations are real....? here are the Fanoutviolation info... ---------------------------------------- *info: there are 121 max fanout load violations...
  4. n.suresh60

    ir drop analysis in physical design

    *how do we know what is the toggle rate for the design.? *on what basis we estimate toggle rate? help me out in ir drop analysis.
  5. n.suresh60

    [SOLVED] how to start hierarchical full chip implementation in encounter or ic compiler?

    Hi all, anyone describe about how to start a chip implementation in a hierarchical top down flow? like *how to partition the design, *how to do time Budgeting, * how to do parallel top level sta, and block level sta, * how to implement full chip with effective way with considering all the...
  6. n.suresh60

    is there any separate group available for the TCL/TK for vlsi automatin?

    hi , is there any group in edaboard for tcl/tk programmars? if know just share it..
  7. n.suresh60

    what is the difference between DEF, LEF and GDS formats ?

    how to differentiate above three, can anyone brief it.
  8. n.suresh60

    How standard cell characterised for Timing and power?

    yes but i want some examples theoritically calculating cell delay with considering corners..
  9. n.suresh60

    How standard cell characterised for Timing and power?

    thanks@jbeniston and i also need information on how exactly the timing and power characterization is done.? for example: how a cell delay is calculated based on the reference pins. and same for power?
  10. n.suresh60

    How standard cell characterised for Timing and power?

    I'm not running tools. I'm a pd engineer, i want to know about how characterization is done for the standard cells. and .lib format
  11. n.suresh60

    Schematic for AOI32,AOI 222 and oai 222?

    You can refer to the following http://www.vlsitechnology.org/html/cells/rgalib013/oai21.html[/URL]
  12. n.suresh60

    How standard cell characterised for Timing and power?

    Can anybody give details on standard cell characterisation for timing and power, if have any document share . thanks in advance..
  13. n.suresh60

    how to convert .lib files to .db files in ic compiler.. i got an warnings check image

    solve this issue. how to convert .lib file to .db file in ic compiler
  14. n.suresh60

    How Welltaps avoids Latch up in chip? please explain ?

    after powerplanning we add welltaps in core area to avoid latchup and well continuity. but i dont know how welltaps going to avoid latch up condition?
  15. n.suresh60

    about Signal Integrity analysis in Encounter ?

    i dont have .cdb files. any other way to do it..?
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