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Recent content by n.mehr

  1. N

    help me in error i found in my vhdl code

    i use ns too and i pressing run key but i donot see anythings
  2. N

    help me in error i found in my vhdl code

    i put picture of errors iwrite test bench but i cant see eny wave i must see wave like this picture
  3. N

    help me in error i found in my vhdl code

    i write a program it is compile. i write 4 test bench for my program and all test bench are compite. but i cant see any wave why?? please help me this is error for test bench 1 see Bottom of Page and this is my code for test bench 1 library ieee; use ieee.std_logic_1164.all; use...
  4. N

    help me in error i found in my vhdl code

    thanks for all Guidance I've solved some of the problems
  5. N

    help me in error i found in my vhdl code

    i can not underestand. errors are for this code: d_out<=Ram1(rd_addr); d_out<=Ram2(rd_addr); Ram1(wr_addr)<= d_in; Ram2(wr_addr)<=d_in; what shold i do? i have 2 process .in read process ,i want if Conditions are corect ,run this code ( d_out<=Ram1(rd_addr); d_out<=Ram2(rd_addr); ) and...
  6. N

    help me in error i found in my vhdl code

    your means is i must define 2 d_out in my component?? like this component Ram is port( d_in :in std_logic_vector(0 to 7); d_out1 :out std_logic_vector(0 to 7); d_out2 :out std_logic_vector(0 to 7); wr_clk,rd_clk :in std_logic ; wr_en,rd_en:in std_logic...
  7. N

    help me in error i found in my vhdl code

    You do not look too closely please see it . 've worked very hard . i use port map Ram1 : component Ram port map (d_in =>d_in,d_out=>d_out,wr_en=>wr_en1,rd_en=>rd_en1,wr_addr=>wr_addr,rd_addr=>rd_addr,wr_clk=>wr_clk,rd_clk=>rd_clk); Ram2 :component Ram port map...
  8. N

    help me in error i found in my vhdl code

    sorry did you see my last code??? i dont use integer and bit vector Gender of index for std_logic_vector is natural .is'nt it? these errors are for this codes: d_out<=Ram1(rd_addr); d_out<=Ram2(rd_addr); Ram1(wr_addr)<= d_in; Ram2(wr_addr)<=d_in; i Define d_out and d_in ,std_logic_vector and...
  9. N

    help me in error i found in my vhdl code

    hello it become better? i Separate processes and i use wait in my processes. becuse in my processes , i give signals value ,i must use resolve sigals then i use std_logic or std_logic vector but i recived this errors what i must do? i know littel vhdl and this is my exercise please hepl me...
  10. N

    help me in error i found in my vhdl code

    I'm studying at the University of Vhdl only for 1 semester It is my practice, and I'll fix it, but I do not know how much Thanks for the tips what a bout this?? this is another program in this program i use + function(sum of two bit_vectors) in package of numeric_bit_unsigned but my program cant...
  11. N

    help me in error i found in my vhdl code

    i dont Understand I've isolated process i use std_logic becuse in errors i see Nonresolved signal.it Was worse my errors ** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(38): Signal "wr_en1" is type ieee.std_logic_1164.std_logic; expecting type std.standard.bit. ** Error...
  12. N

    help me in error i found in my vhdl code

    hello i Receive this errors please help me This is very urgent ** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/dual_buffer/dualbuffer.vhd(50): Cannot resolve indexed name as type std.standard.bit_vector. ** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/dual_buffer/dualbuffer.vhd(69)...
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