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There are many ways to do this. #1) Create a microblaze processor with a UART port. Write software to send whatever commands you want. #2) Create an instance of the UART controller. Write a state machine to control the UART controller with whatever commands you want.
How do you plan to represent the output data? some sort of fixed point notation? Or floating point? If 111 is 7, then 1/7 is something like .14, so what would you expect the actual output to be?
startup clock options
1) I've never used User Mode before, but I think you can generate the startup clock inside the FPGA user logic if you want to.
2) Yeah I'm talking about an external flash memory where you would store the FPGA configuration
startup clock options
It is the clock used during the FPGA configuration process that determines when the FPGA switches from configuration mode to user mode. So if you are going to configure the FPGA out of the external flash, for instance, you would use the CCLK. See the configuration guide...
I agree this won't have anything to do with synthesis. You can load it in the test bench. If you want to load it in the actual module for some reason you can do it by passing a parameter. Here is the parameter syntax in case you are not familiar.
**broken link removed**
Adding SSRAM to FPGA
I am thinking that you are going to want to use the PLL output clock to connect the SSRAM. Since the CPU is most likely being clocked off the PLL clock you are going to want them to be in the same clock domain.
Otherwise you have to create a wrapper type module and then...
Adding SSRAM to FPGA
Actually, have you looked at the example projects that come with the NEEK? I know some of these will use the built in SSRAM. Specifically I have used the projects for the uCLinux distribution. You should be able to look at how the SSRAM clock is connected in these projects...
Adding SSRAM to FPGA
Dora,
The way I have done this before is by creating a top level HDL module to encapsulate the SOPC builder project. That way you can add other logic on the outside of the SOPC project if you desire and you can do things like route the SSRAM clock. You could also create the...
2-bit fulladder
It is [4:0] because if you add together two 4 bit numbers, you may get a 5 bit number. Consider the case of 0xF + 0x1. The solution to this is 0x10 which is 5 bits. There are a couple of ways of dealing with this. One way is to set an overflow bit. Another way is to have the...
All the examples in this thread use the case statement for the next state logic. I would say this is the preferred way to code this logic since it will synthesize to parallel logic. An if else structure on the next state logic describe a prioritized structure.
Well the FPGA type determines the size of the configuration file. Larger FPGAs have larger configuration files. It also depends on how you will configure the FPGA. If you are using a serial loader from a SPI flash device, then the reconfiguration time just depends on the number of bits and the...
What is the A signal? A 1 bit value? The way your counter is setup now it will increase on the positive edge of the clock whenever A is not equal to 0. You may need to refine your if logic.
For instance, create a register for the previous value of A and register it every clock cycle. Then...
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