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Hi ,
I am getting following error. Please someone give idea about this error.
Error:
*E PCIONC expression connected to an 'inout' port must be collapsible..
Interface instance
DDR4_if mic_ddr_if();
Dut instance
ddr_chip ddr4 (.iDDR4(mic_ddr_if))
Below I mentioned the interface file...
Thanks for reply ..
I am doing functional rtl verification. I did not get what you are saying.
I am seeing this script ncsim option (work.tb_top:sv ) in qsys generated ncsim_setup.sh file. tb_top is my top module name. But remaining options ?
Hi All,
Please anyone explain the following ncsim option.
ncsim lib.cell:view
My script is ncsim work.tb_top:sv
Here work default library for design. tb_top is top module .what is view option(module,sv). What is the exact meaning of the above option. I am a...
Thanks for your reply. Actually master data width is 256 so we can send maximum 256 bit data. If we want to send 512 bit data i have to follow 0x20 .
Is it correct ? I am getting confuse with this.
How can i send 512 bit data to the slave from the master(256 bit data width)
Thanks
venkat
Hi All,
I am having 256 bit data width and 64 bit address width avalon bfm master and 512 bit data width 30 bit slave.In between i have one interconnect.
The base address is 64'h 0000_0010_0000_0000(Byte addressable) .while i am sending the data to the 512 bit slave next address range is what...
Hi all,
I need information about burst write operation in avalon bfm. Below i mentioned the task which i am using.
In that burst_size is 3 and burst_count in each burst is 2.So totally 6 data transaction will happen.But In my case i am getting only three data transacation...
Thanks for reply dpaul. The address range for the slave is 0x0000_0000 to ffff_ffff asper design. I am giving e0 only. It is in the slave address range only. Any way i will try address range between 0x9000_0000 and 0x9010_0000.
Thanks
Venkat
Hi,
Can you please someone explain the following warning.
AAXI_WARN: slave0@20548811.0 ps : Write bad address 'h000000e0, will return SLVERR. Configured address is below:
Address in FIFO: [0] 5a43, [1] 5a46,
cfg_info.base_address[0], cfg_info.limit_address[0]: [90000000...
Hi,
In NCSIM i am facing some error in elaboration phase.
ERROR:- ncelab: *F,NOCUF: Cannot Load Compilation Unit.
Elaboration Script:
# elaborate top level design
if [ $SKIP_ELAB -eq 0 ]; then
export GENERIC_PARAM_COMPAT_CHECK=1
ncelab -access +w+r+c -namemap_mixgen...
Hi,
I am running the ncsim.In that I am getting unresolved module error.
ERROR- ncelab: *E,CUVMUR (../altera_emif_mem_model_core_ddr4_161/sim/altera_emif_ddrx_model_per_device.sv,283|12):
instance 'ed_sim.mem.core.pp_gen[0].inst.depth_gen[0].mem_inst.gen_ddr4_rcd_chip.inst' of...
My working folder contains ncsim_setup.sh,hdl.var,cds_lib files.Snapshot is not found means what?
Simulation commands in the script:
if [ $SKIP_SIM -eq 0 ];
then
eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
eval ncsim work.ed_sim:module +avery_new_sparse...
Hi,
Thanks for reply,I am new to NCSIM.I am simulating Quartus generated External memory interface example design.
In that i am using ncsim_setup.sh file for simulation.
Compilation and Elaboration done properly.In Simulation phase i am getting error.
ERROR--- ncsim: *F,NOSNAP...
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