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Some low power techniques are Clock Gating and Power Gating.
Refer to these posts:
1) https://vlsi-soc.blogspot.in/2012/08/clock-gating-integrated-cell.html
2) https://vlsi-soc.blogspot.in/2012/07/clock-gating.html
3) https://vlsi-soc.blogspot.in/2012/08/power-gating.html
4)...
Power Gating has been explained here. Please refer to this post: https://vlsi-soc.blogspot.in/2012/08/power-gating.html
And this: https://vlsi-soc.blogspot.in/2013/03/state-retention-power-gating.html
While transferring data from a slower domain to faster domain, we can clock gate the faster clock every alternate cycle. This is same as a multicycle path of 2. But it is all governed by the architectural requirements. A sneak peek into multicycle paths can be found here...
That is an ambiguous question. I think you mean something else. Latency can be computed by any timing tool, or you can also see it in the timing path. For detailed info: refer https://vlsi-soc.blogspot.in/2013/04/clock-jargon-important-terms.html
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