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incisive debussy waveform dump
From within the synopsys DC environment
you can compile your systemc file with the following command
compile_systemc my_design.cpp
The output is in .db format. If you need the output in Verilog or VHDL format you enter the command
compile_systemc -format {db...
Re: Synopsys- Synthesis
As regards the reply z81203..
I think etherios means how to force DC to synthesize using 1-bit Full Adder cell from the physical library, not the synthetic laibray (DW01_add is from Synopsys Designware Libray).
The problem is how to force dc to synythesize the code of...
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