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Recent content by mult

  1. M

    Deep N-well Depletion Regions

    Hello there, could anybody tell me, what happens if two depletion regions of deep N-wells reach each other? Thanks in advance!
  2. M

    Set Rule Deck Variables with Cadence PVS

    Hello there. If PVS DRC/LVS rule deck uses variables (path to command files folder, metal option, etc. ) then is it possible to set/modify/store them within Cadence PVS environment? Just like we can set and store such variables in a runset file with Mentor Calibre Interactive (Setup->Set...
  3. M

    Matching of huge devices

    Hi everybody! My design uses huge devices which are high voltage devices. The problem is that I doubt they should be matched in the same way as regular devices. Does it really make sense to apply the same technique for matching (common centroid for example) when dimensions are so large. Please...
  4. M

    How to implement "latch-up" guard rings and prevent parasitic lateral NPN at the same

    Re: How to implement "latch-up" guard rings and prevent parasitic lateral NPN at the VDD is supply pad, and VDD is used to connect N Latchup ring as the highest voltage of the chip.
  5. M

    How to implement "latch-up" guard rings and prevent parasitic lateral NPN at the same

    Re: How to implement "latch-up" guard rings and prevent parasitic lateral NPN at the There is a special section in design rule called "Parasitic ESD Rule": "The Rule defines the minimum spacing between two n-type regions to prevent parasitic lateral npn from turning on and unexpected ESD...
  6. M

    How to implement "latch-up" guard rings and prevent parasitic lateral NPN at the same

    How to implement "latch-up" guard rings and prevent parasitic lateral NPN at the same Hi all. I am trying to create latch-up guard rings for IO "low-side" BJT_36V and HVNMOS_36V according to TSMC BCD 0.18 design rule. And there is a requirement of design rule to keep huge space between two...
  7. M

    Synopsys IC Compiler: customize GUI

    Surely I've learned documentation provided by solvnet.synopsys.com. And I know how to customize "hot keys" as well as "strokes" with gui_set_hotkey, set_gui_stroke_binding, set_gui_stroke_preferences commands. As I understand mouse buttons is neither "hot key" nor "strokes" issue. Unfortunately...
  8. M

    Synopsys IC Compiler: customize GUI

    Thanks. But my question is how to CHANGE gui settings not how to use it. As I am working in several tools at the same time I would like to have the same gui setting for all of them. I am used to ZoomIn with right mouse button and ZoomOut with Ctrl+Z. So my question is how to assign ZoomIn...
  9. M

    Synopsys IC Compiler: customize GUI

    Hi guys. I am novice at ICC. Please help me to adjust this tool to my preferences. How to change settings for View->Mouse Tools->Zoom In Tool? I would like to zoom in the area with holding RIGHT (not left) mouse button when selecting the rectangular area. ("Cadence Virtuoso"-like zoom in)...
  10. M

    In depth understanding for MDK,PDK,FDK,TDK and other design kits.

    Is there any description file for layers? Like, for example, TSMC provides "GDS Layer Usage Description File". Couldn't find something like that in UMC 55nm PDK.
  11. M

    Virtuoso Layout "changedLayer tool0" : how to eliminate from cellview?

    Hello! Please help me to remove "changedLayer tool0" layer from the cellview forever! This annoying layer makes me mad. I am not sure in which stage of layout it has appeared in one of cells, guess after Diva verification tool was used once over the cellview. I tried to clean the cell manually...
  12. M

    Layout-dependent effect: help to recognize.

    Hello all. I am confused by one layout dependent affect. I know about: "Poly-to-Poly Spacing Effect" (=PSE), "Length of Diffusion" (LOD =STI ="Shallow Trench Isolation" effect) "Well Proximity Effect" (WPE). But what may bring into layout the minimum "channel - to - bulk_contact" spacing...
  13. M

    Grounded Deep Nwell purpose?

    Does anybody know the purpose, why sometimes Deep Nwell is connected to Ground not to Power? (No PMOS inside DNW; DNW only acts as isolation of some Ptubs from global Psub) Thanks.
  14. M

    TSMC PDK Stream Layer "ref" (0;0) purpose?

    Hi, does anybody know what is the purpose of "ref" layer, number 0, datatype 0 in TSMC PDK? streamLayers( ;( layer streamNumber dataType translate ) ;( ----- ------------ -------- --------- ) ( ("ref" "drawing") 0 0 t ) This layer appears in GDS file, which is result of TSMC "DUMMY OD...
  15. M

    Number of digits for PCell parameters

    Hi all. I designed PCell using SKILL (for example "Seal ring" with three parameters: "Description", "X Die Dimension", "Y Die Dimension"). As you can see at picture, number of digits in dimension-parameters depend on parameter value. ("X Die Dimension", "Y Die Dimension": Parameter's type -...
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