Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Help needed in VHDL FSM sequence detector 0101
Draw fsm and write VHDL code for a system which has is single bit input x and two single bit outputs Y and Z. output of system is asserted logic 1 to Y and Z when system detects in input stream of serial bits 0111 or 0101 respectively
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.