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Recent content by muhammadasour

  1. M

    RUN Assura LVS for our MOM-cap

    Hi, I am designing a SAR ADC. I designed a MOM-cap for unit capacitor of DAC by myself which is not provided by foundry. I have created a symbol and layout view of capacitor and in an example schematic connect the cap symbol to an inverter and in layout connect inverter layout to the cap layout...
  2. M

    Level Shifters Design

    Hi, If the load of your level shifter is very small(less than Fan out of 4 of inverter) you can remove it, but notice that the more load you have at this node, speed and power will be affected. be careful of level shifter sizing and power if you wanna remove it. I suggest not to remove these...
  3. M

    Level Shifters Design

    Diiarmuid, it won't work, because when you apply 3V to the input of inverter with supply of 5V, both nmos and pmos are on and therefore the output of the inverter does not go down all the way to zero, it will be some intermediate voltage and it will cause the same problem in next gates. cross...
  4. M

    Level Shifters Design

    Hi, the following paper discusses different structures of level shifter. (contention mitigated level shifter proposed). "Level shifter Design for Low power applications" by Manuj Kumar https://airccse.org/journal/jcsit/1010ijcsit09.pdf the sizing depends on your input and output voltage...
  5. M

    How to do CTS for a clock which generated internally by a submodule in SOC Encounter?

    I found how to do that. post here just in case some one else need it. in top module if you are instantiating the clock gen module as following: clk_gen DUT_clkgen (clk_ref_xd, ....) in clock tree spec file recall it as following: DUT_clkgen/clk_ref_xd
  6. M

    How to do CTS for a clock which generated internally by a submodule in SOC Encounter?

    Hi All, As you may see in the following clocktree scpec file, clk_ref and reset is input pins, but clk_ref_xd is generated internally by a clock generator submodule. So the SOC shows error on the clk_ref_xd saying it is not a input pin. What should I do? Thanks for your advice ClkGroup + clk_ref...
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