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Recent content by mswug

  1. M

    What is this circuit ?

    what the ckt is? It should be a ESD protection circuit. The right MOS size is very large? And the RC and Inverter is a ESD zap detect circuit.
  2. M

    use ptat current for opamp

    perhaps you can use the current Igm which bias the input device, generates another current Iro to bias the output device. The relationship between Igm and Iro is, Iro=Ksqrt(Igm).
  3. M

    is ESD protection cell provided directly by the library?

    Generally, ESD protection circuit are combined with IO cell. You can get them from foundry that are silicon proven to pass ESD standards.
  4. M

    what is the purpose of these transostors..?

    if it is the option device, it should be dummy with all nodes tieing to VDD or VSS. So Humungus' idea is more sensible.
  5. M

    question on worst cases simulation

    For Worst case simulation, you should be sure that the bias, dc result, ac response are in the range that specified in your design spec.
  6. M

    About line regulation of LDO

    Perhaps your EA gain is changed because some transistors are not in saturation region. You should check your bias circuit to confirm it
  7. M

    Can anyone tell me how to design a level shift buffer?Thanks

    Actually, you should pay your attention to the balance between rising timing and falling timing
  8. M

    EMC improvement for LDO

    Now I have a project to improve EMC immunity for a LDO, How can I to improve it? A customer have a MCU chip want to use our IP( LDO). However, the application envirement has a motor that generates EMC. So they want us to improve EMC le immunity of our LDO ip, but for cost controlling they want...
  9. M

    Help!!!What is "pwell soft connected", a DRC error

    It seems you have two grouds: VSS1 and VSS2. If there is only PSUB, DRC will give a violation"pwell soft connected". you should add PSUB2 to isolate the two ground.
  10. M

    How to Calculate Metal Widths to Avoid Electromigration

    calaulate metal width vs current mdcui is right~~ And for different temperature, there is a coeffient in DRC file. So you can get other temperature electromigration by the coeffient multiple 110 degree electromigration
  11. M

    Question on the ESD protection failed test

    Re: ESD help Hello Chang, 1) For IO to IO (digital) ESD, NMOS of output driver is the key device for ESD zap. So, the negative and positive modes are both failed shows that the output inverter driver should be re-configured or layout it carefully. Failure analysis is good method to find the...
  12. M

    what is limiting amplifier?

    Perheps, you should describe your qestion more detailly. And did you metion Amplifier's spec and their tradeoff between each other?
  13. M

    About Current Reference

    band gap is a good choice for you
  14. M

    how can i get the output of regulator stable?

    it is a full integrated LDO, so do you compensate your LDO with miller capacitor or DFC?
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