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Recent content by msv91280

  1. M

    requet for the Jtag tutorial.

    hi check on fpga4fun.com .In project list You will get detailed information on jtag
  2. M

    Difference between single port and dual port memory

    hi If two processors are connected to Dual port memory ,each one port. If these two reading same memory location there is no problem.But if one read and one wirte at the same time to same memory location ther is problem and also for both writing at same time to same memory location. To...
  3. M

    difference between Baud rate and frequency

    helo What is the difference between Baud rate and frequency .How these two related to bits/Sec ? Can any one explain me? regards msv
  4. M

    delay in verilog program

    hi i cant understand your question ,explain properly or send the FSM code mentioning were you want delay. or else try this: If u want the delay before validating the next state use delay(ie #10) before the particular case statement ie: case() #10 s1:if (present stste==1'b0)...
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