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Verilog instances have sub module ports names after . and in parentheses the connection name is specified. You have just reversed that order.
And yeah, in simulation when you compile a code it will only check for syntax errors. This kind of errors are found at elaboration step. May be you have...
VLSI is a very much vast domain. In my limited knowledge, it includes all of the things that are involved in designing, manufacturing, fabricating and verifying a CMOS chip containing thousands and millions of transistor on a single chip. The designing of a chip to its logic verification then...
Well, as far as I have understood, you wish to find the indices of a memory containing your searched number. Like, if 0-7 are indices of a 8 blocks memory in which each can have a number, now you wish to find the indices containing the number you searched for. This can be done by using Muxes...
Well, you really don't need a circuit element to do that in FPGAs. Just a wire connecting the LSB of the 8-bits number to the ODD Signal. But better help could be provided if you could throw some more light upon your requirements.
MSBR
Well, i recently went through Jan M. Rabaey and N.H Weste book. I found useful info about the VLSI technology there and also these books throw some light on the future of the VLSI Technology. I think that these books could answer your question with much more facts and detail.
Thanks,
MSBR
I think that System Verilog is much more powerful. You can consider learning Randomization, Dynamic Memories, Classes, Programs and Assertions etc for Robust Verification. I agree that picking up a Ready-made design would reduce the designing effort from your end and will allow you to focus on...
IMO, SystemVerilog(SV) is more preferred for verification. Some synthesis tools, though, do support some features of SV for synthesis, but some of its more advanced constructs are not suitable for synthesis. If I were to design a project. I would have gone for the designing in Verilog and the...
I have found a great book regarding the HEVC written by Vivvienne Sze, madhukar Budagavi and Gary J. Sullivan. I have started from there. Also, I am looking into the HM Reference Software provided by the Authors of the Standard. If anyone could provide any further help then I will be highly...
Well, I said ISE infers Dual Port Ram, not instantiates. There is a difference between the two my friend. Once you have written the code for the RAM, you can check whether Dual Port RAM is inferred or not by the ISE by synthesizing your design and checking the module level Resource Utilization...
Could you further explain your system? I think you could use simple switch on one of the fingers which would get pressed when the other finger is touching. But it would be quite easier to give a better suggestion if you could throw some more light on it.
Thanks,
MSBR
Yes jubin007, you can read this way using dual port RAMs. I use Xilinx ISE, which automatically infers the dual port RAM when you assign two different outputs from a single LUT.
MSBR
+Q0.14 is a fixed point format. The + sign indicates that it is an unsigned number and the 0.14 means that there are 0 bits integer bits and 14 mantissa bits. It is just a representation. For example, I have a floating point number 0.0255. In +Q0.14 format, the scaling factor is 2^14. So I need...
Audioguru, But don't you think that as the transistor sizes are shrinking the Voltage and current requirements are reducing and thus the power dissipation is also reducing for each transistor?
I think you can use a +Q0.14 format to store it in Fixed Point format. I used a simple taylor series to generate the quarter wave of the sinusoid. I just used the values in the simulations but you can write it in a text file and then generate some ROM with those initial values.
Once you have...
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