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Recent content by mrothe

  1. M

    VHDL generics: how to make a port of width log2(generic)

    Thank you. I didn't know how easy it is to use my own types; now I know! :smile:
  2. M

    VHDL generics: how to make a port of width log2(generic)

    Thank you. After some trail & error I came up with the following code: library ieee; use ieee.std_logic_1164.all; use ieee.math_real.all; entity top is port ( clk : in std_logic; reset : in std_logic; input : in std_logic_vector(7 downto 0); -- 7 = width - 1...
  3. M

    VHDL generics: how to make a port of width log2(generic)

    Suppose I have an entity that has a generic that sets the width of one input. Now I want to have an output that has the minimum width to address each of the input bits. A 12-bit example follows: entity priority_encoder is port ( input : in std_logic_vector(11 downto 0)...
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