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Why not send an e-mail to one or more of the people doing research? That sort of thing actually has been known to work. ;) They might point you in the right direction.
I'd expect that a 6-bit updown counter will take at least as much power/area as 6-bit upcounter, and possibly a bit more. I'd expect area increase to be slightly more pronounced than power increase. But as TrickyDicky said, try and find out for yourself. :)
You could probe the LCLK or ADCCLK signal to see if you actually get a stable clock there. Seeing your clock signal on an oscilloscope tends to generate "ah hah" moments every now and then. Or if that's not an option for whatever reason you can sample those same signals in chipscope as already...
This should get you started:
https://www.ti.com/lsds/ti/data-converters/analog-to-digital-converter-products.page#p84=8;10&p1089=1000;5000000000
Not that you should use TI per se, but the parametric search should get you some idea of all the options out there.
You should show the code for your mac unit.
Not sure if you should actually be using an assign, but since you ask for it and show no code to base better advice on ... https://www.asic-world.com/verilog/synthesis3.html
Looks like assert is the only statement you need to take care of. Several options:
The "who cares" option. Any decent simulator will handle SV these days. So if your simulator supports SV you could just use SV for your testbench and verilog for sysnthesis.
The "oh alright, I will Read The Fine...
Genius! You incredible ... human, you! Thanks for a good chuckle.
Allow me to paraphrase: "Yes K-J, you are absolutely right. Getting the testbench in order should really be my priority at this stage, because that will make the debugging that much easier now AND in the future. When I have that...
Nope, no C++ required. You only need it when you want to do stuff that is easier to get done in C++ than in SystemVerilog. And I should add that the I only ever used the C++ part for modeling and simulation, not for implementation. That way you can make a working behavioral model with mostly...
*grin* Not only amusing, but too true as well.
In addition to Dave's explanation a 100% personal and thus possibly quite random observation...
Some time ago I tried SystemC along the lines of "mmh, lets see what this can do". The experience was so-so. Maybe due to lack of tools/libraries back...
Nah. He just doctered the paths and then took a screenshot. That's what I'd do to mess with people. XD
Good call. I did notice the ZZZ signal in the testbench, but that was hardly unique given all the Z's. But that warning message is a pretty good hint.
Are you sure it's not expectation value error? As in, I could see how you can confuse yourself easily with the simulateously incrementing counters. The reason I ask is that I don't really see anything problematic with your posted code. Couple of style points, but it looks to be okay. What I...
I can sortof see the point. You have the main testbench, which is so complex that it needs to be checked and may even need debugging. So to check/debug it you need another testbench to check the main one. But this secondary testbench probably can be a lot simpler.
It's is just one step further...
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