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Recent content by mrdotcom1

  1. M

    Can I use Chipscope with ISE webpack 9.1?

    Re: chipscope hello, I think nobody was pretty clear regarding ur issue... Yes theres abslutely no prob if u r using ISE webpack for ChipScopePro
  2. M

    VHDL code required for S Transform

    Can anone please give me the VHDL coding for the S Transform of a signal of +/- 1V. Waiting for the response. Thanks and regards
  3. M

    Help me out with a VHDL code issue

    Re: help required Dear Nandini thanks for the suggession. I am working on that now...
  4. M

    transistor model required

    Can somebody please give me the schematic diagram for the Gaussian noise generator. Thanks and regards
  5. M

    How to design a power supply?

    I need the same simple switch mode power supply circuit diagram and whatever may be the parametres. but should be a valid one. So that I can alter my parametres lateron according my design requirements.
  6. M

    Help me design a PLL in Spice

    can someone help in in desining a PLL on a SPICE platform. Thanks and regards
  7. M

    Help me design a PLL in Spice

    can someone help in in desining a PLL on a SPICE platform. Thanks and regards
  8. M

    Help me out with a VHDL code issue

    Re: help required Dear Sir, Thanks for your reply. But 1st kindly go through the code and then let me know. because while I omit only two lines from this code the rest of the code can be synthesised and even with all other real values. And even I do have few more earlier code where I have...
  9. M

    Help me out with a VHDL code issue

    Dear All, I have got my own VHDL code and inside that when i am writting bd_a:=bd_b1(10); then its ok where bd_a value is 0.0 at this place and its a real variable. But if I write bd_a:=bd_a+bd_b1(10); where as bd_a is still 0.0 it gives me error on synthesis that real operands can not be in...

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