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Recent content by Mr.dal

  1. M

    mix-signal sub layout connection

    Hi, it's a very simple solution. Just make a same lable between AGND and DGND to GND. Only for the LVS.
  2. M

    Error "malformed device nrdip" in TSMC035 when usi

    Re: Error "malformed device nrdip" in TSMC035 when I agree with erikl. And I will give just a comment for you. This malformed device error was created during netlist extraction from layout. So you can find extraction information that is seed region and pin region of each device in the VLW...
  3. M

    Error "malformed device nrdip" in TSMC035 when usi

    Re: Error "malformed device nrdip" in TSMC035 when I have just reviewed this violation and I can give the answer to you. LVS rule deck has option regarding resistor's connection that any resistors have no connection, malformed device errors will be generated. Could you try to give the...
  4. M

    90 nm topology layout rules needed

    Hi! alls, this is PDK developer in Dxxxx company. Most of foundries can not share their PDK whithout any consent. If you can download 90nm Txxx or Uxx's PDK, please share with me. Thanks. ps. I can download Cadnece's 90nm PDK and can share it.
  5. M

    Regarding Virtuoso XL Layout Editor

    Hi, I'm PDK guy and give the answer for you. 1. Is this tool availabe for Windows OS.? ==> Windows will be possible. But most users prefer Linux or Unix than Windows. 2. Right now i am using Mentor graphics tool for layout. Do you think Virtuoso XL Layout Editor has good features than...
  6. M

    How to Layout Deep Nwell in TSMC 0.18um HV technology

    how tsmc 0.18 npn Exactly right. Could you send me the TSMC's PDK? 0.18um rf or 90nm.

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