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Recent content by Mr.Anonymous

  1. M

    verilog interview Ques #1

    assign dout = (din==15)? 15: (din==14)? 14: (din==13)? 13: ..................... (din== 1)? 1:0;
  2. M

    How to synchronize data or signal from different clk domains

    Go to http://www.sunburst-design.com/papers/ and read at least http://www.sunburst-design.com/papers/CummingsSNUG2001SJ_AsyncClk.pdf
  3. M

    are there any visual C++ to VHDL converter out there?

    visual vhdl Mentor Catapult C Synthesis https://www.mentor.com/products/c-based_design/catapult_c_synthesis/index.cfm
  4. M

    Syplify synposium notes

    Yes, all links are good. Thank you!
  5. M

    matlab implementation on hardware?

    Go to **broken link removed**
  6. M

    Error in synthesis with Precision RTL

    Error in synthesis I suppose you have combinatorial loop on this _asynchronous_ design.
  7. M

    Modelsim and Modelsim designer

    http://www.model.com/products/60/default.asp
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