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sstl2
According to revised SSTL2's spec(JESD8-9B), the driver current has been increased from 15.2mA(7.6mA) to 16.2mA(8.1mA).
The power dissipattion is reasonable.
Lightly doped drains
If you are a device engineer, you will know that LDD is only used in NMOS only, not PMOS.
Actually N-LDD(for nmos)&P-LDD(for pmos) are default mask steps in any foundry, especially in advanced process.
I suggest you check the part about resistor definition in lvs command file.
BTW, I don't know if you turn on some options(such as LVS REDUCE SERIES RESISTORS, etc..).
According to this figure, the IO seems to have a internal pull down.Becuase the capability of internal pull down is weak, the transition is slow.
Generally the state change from 1 or 0 to high Z is quick, but it is depend on the IO circuit structure too.
I think the model library file have some errors or it isn't spectre model library but hspice model library. If not, do you have look the model library file? Are there ss,tt,fs,ff sections in liabrary file?
At present, How to simulation the low temperature(such as 77K) circuit in Cadence or Hspice?because the model supplied by the foundry can not support below 200K circuit simulation.Adopt medici?
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