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in the ICFB window type the following command.
leHiUnmarkNet()
then click on the net highlighted.
Or in the layout window, go to the connectivity menu and select the option unmarknet.
Re: Poly Cap capacitor
It is possible only if in your process you have two poly layers generally named as poly1 and poly2.
Then only we can construct a poly to poly capacitor.
Out of these u can use ABBA or BAAB as the common centroid matching pair.
Because if u see carefully u will find that the chirality is not proper.
And also the edge effects due to eitching are also similar on them in these cases.
Here if u see AABB or BBAA or ABAB or BABA they are not even...
Re: IC LAYOUT
I sugest u to go through the art of lay out or lee baker.
These are too good for the layout skills.
But simultaneously u have to do practice and start doing layout also.
This is a biasing circuit.
And will be used for current bias.
I think the diode connected should be placed in the middle so that there will be equal distribution of current to all other.
Yes u can calculate the width using the above procedure.
But, remember always give atleast 205 more than the minimum required.
and, for the power lines take as much as u can.
I think if u know how to write a code u can write the test bench easily.
Or,
In a simplistic manner for very small ckts. u can just put the different input values at different times by invoking the actual design in ur test bench but it is not the good way.
I suggest u to generate a random number...
Schematics does not give the fab anything related to the Layers that has to be fabricated.
It is the layout that goes to the Fab for fabrication.
Layout u can say is the drawing thatrepresents schematic in a way that it will fulfill all the functionality and the parasitic related issues when...
I suggest u to first go through the Basics of timing power and clock synthesis.
If u have ur basics clear u will come to know what the tool is exactly doin.
Other then this at ur levevl i think u peop;e are doing very small assignments.
But coming to vast projects it becomes almost impossible...
Re: VHDL
I Suggest u to go through the basic books like J.Bhasker, Douglus Perry etc.
You can get the soft copy og these books in EDA form only.
Just search and download them for ur use.
mcse vs cisco
Ceaser is right.
My opinion to you is first go for the CCNa and then try for MCSE.
You can go for these courses simultaneously with ur job also.
Added after 53 seconds:
Ceaser is right.
My opinion to you is first go for the CCNa and then try for MCSE. You can go for these...
Re: DSP-FPGA
I think u ned to be clear about the DSP algorihtms and have a gud knowledge of any one of the HDLS.
I believe this is enough.
Implementing any DSP algorithm in FPGA require sound knowledge of that Algorithm and the way to implement that algorithm using HDL.
I did the FIR filter...
back end testing of asic
In ASIC back end the we do floor plan, placement, layout and then simulations for checking the correct functionality and timing, parasitics etc.
at last it is delievered to fab for manufacturing.
in simple terms u can say after synthesis everything comes in Backend
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