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Recent content by mostafa_amer

  1. M

    hi ineed help - a weight converter how to start?

    hi ineed help. please provide some more information about the project and the requirements\ Best regards, Mostafa Amer
  2. M

    Need Help in vhdl Code for input+100 points for working code

    Re: Need Help in vhdl Code for input+100 points for working Hi, These are two modules one for input and the other for output, also ther's a package contains constants for bus widths (set to 128 and 32). I've done bihavioral simulation and they work fine but please test them again and let me...
  3. M

    how to display on LCD of FPGA board?

    u may refer to Spartan-3E starter kit initial design (in the reference designs section) It uses a PicoBlaze to display a set of characters on the LCD besides some other interesting functions best regards, Mostafa Amer
  4. M

    microblaze spartan 3 vhdl routines needed!!

    Hi, why don't you consider using PicoBlaze? Unless you aim to implement other complicated tasks,PicoBlaze will be very convenient for you. You may check this **broken link removed** best regards, Mostafa M. Amer
  5. M

    Minimum Of N Numbers using verilog or VHDL

    Re: Minimum Of N Numbers u r wellcome ps: the whole tree may be synchronized but that'll affect the overall clock speed, u may consider the pipelined architecture BUT if ur solution works fine, hold for it :)
  6. M

    Minimum Of N Numbers using verilog or VHDL

    Re: Minimum Of N Numbers hmmm in such a case u may consider the other extreme; do not use resource sharing at all and build a comparator tree with (log2 N) levels and (N-1) 8-bit LT comparators. a pure combinatorial circuit . and if multiple N-numbers sets are applied you may use pipelined...
  7. M

    Minimum Of N Numbers using verilog or VHDL

    Re: Minimum Of N Numbers Dear kalyansumankv , You said Numbers are not saved in memory => They are introduced to the core sequentially => I assumed that they will be introduced a number at each cycle => Introduction of numbers will take N cycles => If getting the minimum took less than N...
  8. M

    Minimum Of N Numbers using verilog or VHDL

    Re: Minimum Of N Numbers HI, below is a VHDL code that accepts a stream of 8-bit unsigned numbers and output the minimum of the introduced stream. It contains a register (min) to hold the minimum value. This register is initialized to the maximum possible value ,255, when the ENA input is...
  9. M

    Neural network with spartan 3e for speech recognition

    Hi I've worked on a Hopefield network, so if you can explain your design and your problems throughly we may help. What is the range of the inputs. How is your network organized? what exactly are your problems? Best Regards, Mostafa Amer
  10. M

    FPGA/ CPLD as a substitute for Microcontroller?

    dip cpld I think FPGA is suitable for more complicated applications. Some application resides in the grey area between them and micros, in such a case u v to decide which technology to use. About switching, it will not be complete switching as I said before different applications will need...
  11. M

    Minimum Of N Numbers using verilog or VHDL

    Re: Minimum Of N Numbers It could be done BUT [1] Is N fixed or variable? [2] What is the bit length of the numbers? [3] How are they represented?signed or unsigned? [4] Is there any constraints on the number of clock cycles needed to compute the minimum? [5] Are the numbers stored in a memory...
  12. M

    VLSI job market in Middle East

    expected salary for sysdsoft Hi I am a fresh graduate :) finished my military service this month :) and started looking for a job :) During my graduation project and my military service period, I have acquired FPGA designing skills and learned to use different tools from Xilinx. I would...
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