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Recent content by mooner

  1. M

    Can somebody tell me how to generate sdc file?

    Re: SDC file You can type command in dc_shell: write_sdc your_file.sdc
  2. M

    n Design compiler,how to transfer verilog file my.v into schematic view with tech my

    In Design compiler,how to transfer verilog file my.v into schematic view with tech my Hi: Anyone can Help me that in design compiler, how to transfer verilog file my.v into schematic view with technology myself,e.g.,tsmc,but not synopsis provide? I add target library and link library with tsmc...
  3. M

    How to define for "Freq" and "Noise" of vdc source in analogLib , cadence

    Re: How to define for "Freq" and "Noise" of vdc source in analogLib , cadence I see. HF.
  4. M

    How to define for "Freq" and "Noise" of vdc source in analogLib , cadence

    Re: How to define for "Freq" and "Noise" of vdc source in analogLib , cadence thanks! but how to use VCO_workshop? i have thought that it is a doc, but it seems like a software, when i unzip it. BTW, what's the meaning of HTH? ---------- Post added at 03:24 ---------- Previous post was at...
  5. M

    typical value of Charge pump current?

    whether 5uA is too small? when VCO produce 2.5G frequency, and three order passive LPF, provided osc input 10M frequency?
  6. M

    How to define for "Freq" and "Noise" of vdc source in analogLib , cadence

    How to define for "Freq" and "Noise" of vdc source in analogLib , cadence when i do phasenoise simulation in VCO, i find that filling some value in "freq" and "noise" for example 1 and 1, the result of phasenoise entirely changed. So i doubt what value in those box is reasonable. the doc of...
  7. M

    how to write script in cadence?

    doing same simulation but on the different corner for example, make the key in the ADE for Normal, Fast, Slow to be rechoosed time and time by my hand and eyes, so I have to stay there to monitor. Added after 3 minutes: Thanks a lot !
  8. M

    how to write script in cadence?

    scripting in cadence because when I use cadence for example ADE to run simulation, some actions are always repeated and my hand is needed to control it everytime, so I want to study scripts to make the machine auto execute simulation. It is said that skills in cadence seem like to do it, but I...
  9. M

    How to simulate different block of PLL for noise ?

    PLL noise simulation Yes, I find it . thanks bill_sun.
  10. M

    PLL: Regarding Charge pump

    only simulate the VCO to check that when control voltage equals to 1.5, whether the VCO frequency could need the requiment ?
  11. M

    How to know the noise floor level or the corner frequency in PSS?

    Phase noise in PSS the corner of noise floor is about 30M in my ring vco
  12. M

    How to simulate different block of PLL for noise ?

    PLL noise simulation hi, bill_sun, would you please tell me that where the "pllLib" is in detail?
  13. M

    typical value of Charge pump current?

    what's the Vth of this process? Vth of Nmos is 0.6~0.7V in generally, i know. so the spec 0.5V is too small. in addition, your current maybe changed into low voltage type other than your diode connection.
  14. M

    ask for proper solution for this synthesizer

    solution phase synthesizer from 100M to 400m, how to multiply?

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