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@dpaul
Thank you for your reply.
I got where I did the mistake. I am doing OSERDES-ISERDES loopback. There should be a delay between the reset release and asserting OCE(output clock enable of OSERDESE2). The delay which I have given for OCE wasn't sufficient. So I increased the delay much more...
Hi,
I have been working on 7-series FPGA where I need to implement ISERDESE2 primitive. I am not getting any output out if it. Earlier I have implemented ISERDES2 on 6-series FPGA without bitslip operation. It was working. Now ISERDESE2 is not working. I understood Bitslip is for data alignment...
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