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Recent content by moneychaser

  1. M

    interview questions(contd...)

    4) base layers are pre-fabbed 5) performance, power, area, faster P&R
  2. M

    How to deal with memory in a processor?

    Artisan (**broken link removed**) do a free memory compiler for TSMC .18
  3. M

    Synthesis Help:in verilog codes

    $readmemb is only synthesizable with Synplify. No other tool will synthesize it as far as I know.
  4. M

    Interface between ZigBee silicon and microcontroller parts

    For OKI (ml7065) and Integration (ia4451) parts, the interface is to the MAC and ZigBee is SPI. For ChipCon cc2420 & Ember em2420, all software is implemented on an external MCU, with an SPI interface to the PHY / RF. ChipCon, Ember and Jennic now have SoCs that have the MCU integrated on same...
  5. M

    What does flipchip design mean?

    what is flipchip design There are two main differences between wire-bond and flip chip. - In wirebond, the I/O pads are placed around the die. In flip-chip, they are placed all over the die. - In wirebond, the die has the top metal layer facing up, in flip chip, the die is flipped upside...
  6. M

    Help me to estimate die size for chip in 0.13 process

    estimating die size Area is mainly down to the standard cell library you use, rather than foundry. For example, if you use Artisan Sage-X libaraies, die size will be the same for 0.13 for any fab (TSMC / Chartered / IBM / UMC). However, if you use Artisan Metro libraries, die size will be...
  7. M

    How to design the baseband with Bluetooth?

    on the BLUETOOTH Spec is available here: **broken link removed**
  8. M

    about gatecout at .13 & .18 TSMC process

    For high fan out nets, a lot of buffering may have been inserted for .18. But as you set_dont_touch for .13, that buffering may not have been inserted, resulting in a smaller design.
  9. M

    Where to download Dc binary

    It can be downloaded from SolvNet: https://solvnet.synopsys.com/amserver/UI/Login Or directly from FTP site. ftp://ftp.synopsys.com
  10. M

    how to write a memory bist module?

    If you want to write the actual BIST logic from scratch (i.e. not use someone elses code), the you need to web search for the "March G" algorithm. Look for a paper by AJ van de Goor. Most March tests are for bit oriented memory, so also look for his paper about word-orientated March tests.
  11. M

    Nee tips for ARM ALU designing

    help: ARM ALU design The trick to designing a good ARM ALU is to put the barrel-shifter for the second operand in a different pipeline stage to the adder.
  12. M

    Issues concerning synthesis library usage

    synthesis library usage If you have Artisan libraries, you can just load the Synopsys .lib libraries (i.e. sc/synopsys/slow.lib) into PKS using the read_dotlib command.
  13. M

    Have you ever implement MP3 decoder in FPGA without DSP?

    mp3 decoder Have a look here too: **broken link removed**
  14. M

    Anyone has done MP3 decoder in FPGA?

    MP3 decoder in FPGA? Have you seen this? **broken link removed**
  15. M

    verilog code of a pipelined adder

    Pipeline implementation Take your combinational logic, and insert banks of registers between it.
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