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Recent content by mondobongo

  1. M

    Help me convert VHDL code to Verilog

    Re: vhdl to verilog thanks nand_gates so I don't have to convert a register to an integer to use in bracket in verilog but in vhdl i have to
  2. M

    Help me convert VHDL code to Verilog

    how can i convert this code to verilog... I didn't understand... process (Reset,Clk) variable RegBit :integer range 0 to 13; begin RegBit := conv_integer(BitCountPar); if (nReset = '0')then Data <= '0'; elsif (Clk'event and Clk = '0')then if (EnableStrobe = '1')then...
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