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actually I have given Vss supply to nmos current mirrors of first two differential stages.
And gnd is given to latch output stage.
Will this cause problem?
Hello s
I have designed a schematic and layout of dual input dual output comparator. I have completed Dry run successfully. But facing errors in lvs run.
Screenshots of errors and layout is attached with it..
Plz help me with a solution.
These are the screen shots
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