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Recent content by moira

  1. moira

    floorplanning...in altera....

    floorplanning...in @ltera.... have u tried to use quartusii? maybe ok
  2. moira

    SDRAM controller use CPLD

    use sdram controller from xess there're lots of files abt SDRAM controller on the internet, i'v seen some of them, none of them can be used in my project. in my project, CPLD functions: 1. receive data(8-bit parallel) from 89c52, 2. write and read sdram(1Mx4Banksx16bits), the address and...
  3. moira

    whose work is on layout too?

    i'm newbie, and i've designed some double-layer board
  4. moira

    A question about Protel DXP 2004...

    A question about P*otel DXP 2004... i installed 2004,but i don't like it. it's complicated.and i can't bear with the startup procedure. and ,i think,yes, u need the nanoboard
  5. moira

    Where can I find info about CANBUS protocol?

    Re: CANBUS protocol i know noting abt CAN,but i've downloaded the spec
  6. moira

    need driver source code of WLAN USB Adapter

    anyone has the driver source code of WLAN USB Adapter? or some reference abt it, if u have,pls send me, thk. moira
  7. moira

    Problem when programming Max7000S with JTAG

    unrecognized device or socket is empty pof datei have u installed the driver? if u use WIN2k or WINXP,u must install the driver . i use EPM7128SLC84-15,too.
  8. moira

    help needed for Multicycle Hold timing assignment-quartus3.0

    could u paste ur code ? single process for it ?
  9. moira

    How to protect the I/O port of my FPGA ?

    buffer u mean,u just want to make sure which package of FPGA u should choose, don't u? or to design a protect ciucuit? if package of FPGA, i suggest PLCC, well, u could use a chip carrie socket for PLCC. in my design ,i use CPLD,EPM7128SLC84, for removing it expediently,i bought a PLCC...
  10. moira

    need help from vhdl developer?

    or can not have such operands in this context u want to generate the timing of VGA,right? i've written one that is similar to urs,according to ITU- RBT 601,and i use quartusii . i couldn't understand ur code. u could write me ,and we can discuss it
  11. moira

    how to generate 10M input to the CLKIN pin?

    if u need 10mhz crystal, i don't think the resistor is necessary. and if th dependability of ur system is required very strict, i suggest Voltage Controlled Crystal Oscillator (VCO, 4 pins).
  12. moira

    How does a D-FF function?

    in cpld/fpga, u can use dff to implement dividing frequency, and Jitter-Eliminating circuit
  13. moira

    How to produce time delays using VHDL?

    Re: using time delay after is useless for synthesizing. i've seen an article abt how to delay. the high frequency clk will be used to drive a shift register, the input is the signal u want to delay, configurating the register according to the delay time of the signal. the output is the delay...
  14. moira

    Can we convert composite into analoge RGB using fpga

    convert composite to rgb could fpga do d/a conversion?

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