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Recent content by mohamed_shfat

  1. M

    FFT core design on FPGA board

    Thanks for the reply sir I want to achieve the best correct data streaming and controlling the FFT core, may you please explain me how can i connect the FFT and FIFO streaming interface easly. And thanks too much
  2. M

    FFT core design on FPGA board

    Ok sir, may you please just tell me how can i use it at the input of the FFT, can use AXI Stream for FIFO and connect the handshake ports (Ready - Valid) directly to the FFT's handshake input ports or not. Thanks for everything
  3. M

    FFT core design on FPGA board

    First thanks for your reply sir :wink: My question here was just about a part of my design which the best way to connect the asynchronous FIFO with FFT core. I asked if someone had an idea or did it before may help me to do it and tell me how it can be done perfectly. Regards
  4. M

    FFT core design on FPGA board

    FFT and FIFO synchronization in FPGA Greetings everyone Can anyone please help me and tell me how can I use the FIFO memory IP CORE to synchronize and control my FFT core. Recently I did a small research about controlling the FFT IP CORE v9.0 and I found many users who has used the FIFO as a...
  5. M

    FFT core design on FPGA board

    Greetings all I'm here new to the FPGA world and the HDL as well, i'm trying to implement some FFT core function on my Arty 7 FPGA board used the verilog language, but unfortunately i'm facing a lot of problems to control this core and make it work successfully. My question here is about the...
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