Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi all,
Is it possible to incorporate the Xilinx TFT controller IP in the spartan 3E 1600 starter board. ? I would like to use this controller to interface it directly with a monitor using the standard 15 pin VGA port since the IP has support for the VGA interface as well.
However, the issue...
WARNING:Xst:2042 - Unit bidir: 8 internal tristates are replaced by logic (pull-up yes): bidir<0>, bidir<1>, bidir<2>, bidir<3>, bidir<4>, bidir<5>, bidir<6>, bidir<7>.
INFO:Xst:2261 - The FF/Latch <t2/b_0> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/b_0>...
Hi,
I am planning to implement a router mesh network inside the FPGA with bidirectional buses. Unfortunately , it seems that tristating logic is not available for internal signals.
Could anyone kindly suggest any ideas by which an internal bidirectional bus can be implemented ?
I read...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.