Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
he high-frequency common-mode feedback
Miline7 is totaly right !
OMEsystem poles come from the Mos 's gate (Grid) , so you will compesate this pole by the shunt capacitor .
Re: hi,can anybody afford me some papers about Doherty ampli
Well
I don't know who better than Doherty may explain better the Doherty amplifier !
So I download this historical article by Doherty himself
By the way May someone may help me to find this article (I try to do a linear RF...
Hello ,
I have just a question concerning RF linear amplifier
I know the problem with feedbak due to delay , nevertheless in the past (for example in Radar) ,feedback was used .:!::!:
I know Cherry did a study on this problem. (in Audio amplifier people can hear this)
May you try to explain...
LEVELS shifting
Hello husseindal,
take a loock on jerryzhao's schematic , the second one "tries" to cut the path between the Avdd 3.3 volt to the ground so it means it's the faster one.
On my point of view you can use the second one up to some 100 MHz without any problem (good duty cycle) ...
Hi Butterfish
I agree with you , off course theChrystal needs to be remove from the netlist for the negative resistance measurement.
Concerning the DC operating point , because we are in positive feedback (oscillator and by the way negative impedance ) I don't understand how we can get a...
A OPAMP design
As Montage3000 told you : "put your main pole at the output "
it means the most suitable amplifier for your requierement (as I saw actually) is a OTA.
Hello Davidwong
I guess butterfish tell you to suppress your crystal into your netlist (of course you don't have it in your schematic)
Between the nodes called X1 and X2 (where you will put your crystal) and keeping your external capacitors, you put an AC voltage equal to 1 on your schematic...
Hum
remember what is the Laplace transforme of capacitor is something as 1/Cs with s=jw
Now if you use a logarithmique scale (as Bode plot) what do you get ?
-20 Log(w)-20Log(C) (So a draw in a X logarithmique scale).Nevertheless you need to polarize your PMOS Capacitor before to perform this...
Ok ,
may you provide the BW and stability of your CMFB ?
I suppose you have a problem with your CMFB , but I need more informations, because when you decrease the imput amplitude of your signal , disymetry is still there.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
