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Hello pini_1,
Thanks for the answer. I checked your page but didn't find anything related to post-synthesis or post-map.
Anyway, I discovered the problem. Except for those two files: 'unisim_VCOMP.vhd' and 'unisim_VPKG.vhd" also the 'primitive' folder with all its contents need to be copied...
Hello everyone,
I'm trying to simulate some Xilinx VHDL design with GHDL. Unfortunately I have some problems. I am using GHDL 0.28 and Xilinx Webpack 11.3. Here is how I try to do it.
I got the post-synthesis file - 'temp_synthesis.vhd' which starts like this:
...
library UNISIM;
use...
Checked that and indeed it wasn't.
It is declared using generics and it took the default value (=0) because I forgot to add it when I did instantiate it in one of the components. But what is strange is that ghdl didn't complain and took the value from the top most component.
Thanks for your...
Hello,
Does anybody know how to deal with this error:
Use of null array on signal <rout_cb.parameters> is not supported.
INTERNAL_ERROR:Xst:cmain.c:3446:1.47
------------
subtype param is std_logic_vector(31 downto 0);
type param_array is array (0 to nrofsensors-1) of param;
type...
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