Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi artmalik, thanks a lot.
I know what you say, and I want to check(re-generate) aocv table by hspice.
But I find a question here. Because the aocv table is generated by what you say.
If we want to calculate the real timing ,it should be
(liberty timing *stage number) * (the aocv data of that...
The delay of a inverter is 20ps,
The aocv table (early) is
1st stage is 0.9
2nd stage is 0.95
3rd stage is 0.97
If there is no aocv table , the timing delay after 3 inverter is 20+20+20=60ps
Or using ocv early =0.9 ,
The timing delay after 3 inverter is 20*0.9 + 20*0.9 + 20*0.9 =...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
