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To cancel one mechanizm of instability by other you have to provide compensation region through whole PVT range, including statistical mismatches. Typically each instability factor is uncorrelating with others.
So many criterial task is very very complex. It have to include a lot of...
To design 1ppm@10MHz non crystal oscillator - unrealistic task from my viewpoint. Even with sophisticated digital calibration. You have to provide a stable (<0.2ppm) electrical reference to allow feedback compensate drift.
Depends on available characterized protection structures. If floating (in N-well) zener diodes with BV=5...8V are available then back-to-back diodes can be used. Mirrored SCR can also be used to provide bipolar protection.
For speed below <10KSPS sigma-gelta ADC is about standard. It provide reliable in noisy environment, accurate and flexible solution, - tardeoff between Resolution/Speed is achieved by digital harware modification only. Best to use 2-nd order SDM & 3-d order decimation filter, but if you have big...
switch has the same type, as current source, because any current mirroring will means increasing of error and speed reduction. Choice between PMOS and NMOS is defined by design tradeoff
All I/O cell are designated to connect internal signals to external world, providing necessary level of protection from ESD (Electrical Static Discharge) or EOS (Elctrical OverStress) events. This is common feature of all I/Os. All other are differences. Digital I/O can't to transfer analog...
most of IC-to-IC, IC-to-apparature interfaces are standartized (see PCI, TTL, CML,... standards in JEDEC documents). They define electrical and logical requirements to physical parts (i.e. I/O) of the interfaces,- like input/output switching levels, loading conditions,... That is why there are...
From analog viewpoint an inverter can be assumed as single-ended comparator with fixed and pure defined threshold voltage, strongly depending on PVT(i.e. Vdd/2+Vos, where Vos(PVT) ~ +/-30%Vdd). To reduce this dependence an offset periodical correction method is used. That is devision a...
A protection have to included into each pin of your IC. Supply pad protection plus diodes protection in each signal pin allow to provide ESD path for any combination of stressed pins.
typically a number of ring oscillator (RO) types are implemented in test chip: ROs with inverters, buffers, gates (nand, nor,...); RO with different fanouts (FO=1, FO=4,...). RO self oscillating frequency at different conditions (i.e. PVT) give a most timing information dealing with library...
grouth of Vth at the low temperatures will increase delay, while mobility increasing produce an opposite effect. Question is where it will ballance each other.
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