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design compiler report_area non-combinatorial
How to get exact number of flip flops after synthesis with design compiler? report_area gives only information about (non)combinatorial area.
MK
Re: ethernet decoder
Designing TCP/IP stack in VHDL is not trivial, usually only MAC layer is done in HDL and TCP/IP in software (also available for 8 bit micros: for eg. uIP).
MAC layer does not need very big FPGA, I've designed fully functional MAC controller full/half duplex 10/100M speed...
vsim fsdb
Hi,
I finally get it work on Win2k (Modelsim + Debussy) on VHDL project:
copy novas_fli.dll from Debussy\share\pli\modelsim_fli54\winnt to
Modeltech\win32\
copy novas.vhd from Debussy\share\pli\modelsim_fli54\winnt to your .\SRC\ directory with other VHDL source files
compile...
USB 2.0 evaluation board
Hi
Do you know about USB 2.0 (PHY only) evaluation boards with FPGA (Xilinx or Altera). Which one to choose?
I know about these:
**broken link removed** (without usb but can connect to usb boards below)
**broken link removed**
http://www.asics.ws/doc/otg2_eval.pdf...
Re: 2D Accelerator ??
2D acceleration could be for eg. hardware line (circle,box) drawing using bresenham, dda or others algorithms; also blitter (block image transfer). You can find some useful information here:
circle :http://www.dcs.gla.ac.uk/research/fpga/papers/pdf/fccm94.pdf
**broken...
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