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thank you for your help
I have another question
we estimate the aera of a block and then use wire load mode accordingly to calculate the timing at pre-layout stage
then after placement ,the detail routing has not been done
how do we calculate the wire load delay ?
it is said that we extract...
do the EDA tools change the netlist during floorplan and placement to meet the timing requirement ？ or just adjust the position of the cells?
if we adjust the position of the cell, what is changed by doing this except the wire and all timing information related to the wire?
what can we do in...
Thanks for your advice
But I am not very clear about how to use initial condition in HSPICE
all I knew is that we can set a Capacitor with a initial Voltage
but i do not know how to use it in the circuit above
I want to simulate a circuit like this
the netlist is as follows
X1 in out1 vcc gnd inverter
X2 out1 out2 vcc gnd inverter
X3 out2 out3 vcc gnd inverter
X4 out3 out4 vcc gnd inverter
X5 out4 in vcc gnd inverter
I want to do a simulation ,that there is a initial pluse as the input of the...
I think my question can be answered here:
Hardware acceleration maps some or all of the components in a software simulation
into a hardware platform specifically designed to speed up certain simulation operations.
Most commonly, the testbench remains running in software, while the actual
design...
There is a SoC ,which use ARM9 as the core,
If we want to design a new functional module on this system ,may be as a slave on the AHB
is it necessary to use FPGA to verify the module ?
and how can this be done?
Do we have to implement whole of the RTL code including ARM core and the new...
hi , you can have a try with the regular expression below.
% set a {atom [7:0]}
atom [7:0]
% regsub -all {(^atom[ \t]*\[)[0-9]+(\:0\])} $a {\17\2} c
1
% puts stdout $c
atom [7:0]
%
cummings fifo
The depth of a FIFO depends on the data processing rate both on the send side and receive side.
The size of a FIFO should takes the "worst data transfer" into consideration.
Generally, the worst situation contains two transfers.
Then the data length of the two transfer should...
Re: [help] FIFO
Thank you ,
I agree with you that the "overflow" and "underflow" will not happen, actually I am thinking of the efficiency of the FIFO,
If the depth of the fifo is 8, the write clock is the same with read clock.(this is just for a simple instance, but we still have the...
A asynchronous FIFO requires synchronizing the write_pointer and read_pointer to the other clock domain for compare.
we compare syn_read_pointer and write_pointer to generate "full signal" , but the syn_read_pointer is not "latest" but 2 clock cycles before . so the "full signal" will be...
Help me this typical APB writing process
which is described like the pic below
please use verilog to write this, thank you
PS:
Here is my code , i did not implement all the function. It is my first time to write RTL code, so I think there might be some misunderstanding to the APB...
what is the difference between "port" and "pin" in DC
if there is a output port in the design named " output " are these commands the same ?
[gets_pins output] [gets_ports output]
Re: DC voltage
DC point is the work point for most of the digital device ,
If you have a look at "Inverter" which is the basic device of the digital circuit
you will get it
at least , a stable dc point is for the stabilization of the system
the turning point is floating if the DC is not stable
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