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in the sequential logic , without else, it is not synthesized latch. But in the combinational logic .it will.
in your combinational code , it is uncorrect. because it will cause combinational loop. i think you can use "assgin" statement replace the always block.
Re: synthesis question
i think you should make period of create_clock less than 16n second. Because after DC, p&r and cts and other design flows will add a little delay.
cadence vs mentor vs synopsys
I use synopsys's tools two years and use cadence's tools only a little time. I like synopsys's PT and VCS, solvnet of synopsys is also very good. I think the tools of cadence is tangled.
The above is individual idea.
best wish!!!
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