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Recent content by mh123sh

  1. M

    PCI Express Gen 2.0 clock

    Hello, what is the PCI Express Gen 2.0 clock logic level, is it LVDS or HCSL? Thanks, MH
  2. M

    layer stackup model in HSPICE

    I am doing SI simulation using HSPICE. the topology is as follows. Driver (ASIC) --> PCB trace --> Receier (ASIC). Total number of layers in PCB: 12 I need to use stripline for simulation. Right now i took inner 4 layers (GND, SIGNAL, SIGNAL, GND) only to model the PCB trace. I am using...
  3. M

    differential signals O/Ps not starting from correct -HSPICE

    Re: differential signals O/Ps not starting from correct -HS P and N means positive and negative signals Added after 11 minutes: Thank you ashish, I got the spice file from other team and got waveform snapshot along with the sp file. In the received waveform the + and - signals starting...
  4. M

    what exactly dielectric thickness in 4layer stackup means?

    Re: what exactly dielectric thickness in 4layer stackup mean Core : a laminate with both sides coated with copper (copper thickness 0.5oz, 1z..) Prepreg: only dielectric material. Prepregs are used stack the cores together. Cores are used to form the inner layers typical 1.6mm (63mil) 4 layer...
  5. M

    differential signals O/Ps not starting from correct -HSPICE

    I am doing transcient analysis for a differential signal using HPSICE. Topology is Tx--> Txline--> Rx. The P and N signals to be started at 0v and 1.2v, but it is observed that the both P and N signals are starting at 800mV. Please help me to resolve this problem. Thanks in advance

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