Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
you should read out the values out of RAM and compare the values to older one, if bigger, store in register, if not throw away or something, you also need somehow the timestamp of the values to calculate the delay....simply as far as i understood from your case....or at least this can give you...
you should download webpack, its free, core generator is also included....webpack has some limitations.... you need to check if its enough for your needs
Hi,
i intend to implement the freq. hopping algorithm(hop selection block) of bluetooth spec. in hardware(i.e im FPGA).
Now, after i checked the related pages in bluetooth spec., i am a bit skeptic if those modulo operations can be implemented in hardware. But, on the otherside there are ICs /...
Hi,
i intend to implement the freq. hopping algorithm(hop selection block) of bluetooth spec. in hardware(i.e im FPGA).
Now, after i checked the related pages in bluetooth spec., i am a bit skeptic if those modulo operations can be implemented in hardware. But, on the otherside there are ICs...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
