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Hey Guys !
I've been woking on this project and i dont know why it does not work....:evil:
its required to make a simple ciphering function for images with any dimension..( just to make its details unclear for example) 8-)
function [op]=cphx(ip)
n= ip([end:-1:1],[end:-1:1],:) ; % flipped...
First of all , thanks again for the super-fast response ;)
well, the following code tells u what i mean by ''other project requirements''
EDIT: its a shift RIGHT register ;)
process(clk)
variable tmp:std_logic_vector(9 downto 0);
variable parity:std_logic;
begin
if(clk'event and...
Hey Guys ! i'm writing a VHDL Code to describe a serial in parallel out shift register -which is not that hard- but the problem is the constraints that's imposed on me by the required project:
its required that if the first bit of the sequence is 1 then the register will begin to recieve data...
hey guys !
i've written a VHDL code and its ready for simulation, i just dont know how to make modelsim use serial values for an input.
example: x=1010110101
can anyone help ?
thanks in advance :)
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