Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi all,
I heard that cubic metric is more meaningful than PAR when characterizing RF amplifier performance. Could anyone explain to me the idea behind cubic metric and how to intrepret it when doing measurement?
Thanks,
mesfet
Hi all,
I saw many ieee papers describing how to improve IIP2 of direct conversion receiver by circuit design and calibration techniques. Since most of the on-chip LNA are differential, a balun is needed. Anyone has any materials on how amplitude and phase mismatches from balun affect reciver...
Hi all,
Anyone knows how to build a DAC in matlab or simulink? Just a basic and simple one is good enough. What I want to experiment is to convert a digital signal to analog signal, and filter it by an analog filter.
Thanks,
cfy30
overflow cic decimator
I read Hogenauer's paper and know every stage should be set to Bmax in order to get bit exact accurate result. This is what I have done on the tapeout.
But there are two things bugging me big time
1. The "paradox". Why...
hogenauer model calculation
Thanks for all the valuable inputs.
Just finished the tapeout code and get a chance to check e-mail. In order ensure the design works, I set all integrators and differentiators to Bmax in this tapeout.
For my design, R=8, M=2, N=4, maximum bit growth = 16bits...
site:www.edaboard.com hogenauer
Thanks the prompt reply. I know setting all the integrator and differentiator to Bmax works fine, as proven in simulation. I am trying to figure out what is the reason behind. What trouble me is the fact that Bmax is the required bitwidth at output, but how come...
setting cic filter bitwidth in simulink
Hi FvM,
I guess your answer is the key to my doubt. Since I am new to DSP, I don't quite understand what "that is allowed to overflow above Bmax bits (in case of 2^n decimation factor)" means. Can you give me an example? or do you have any reference...
cic bit growth
Thanks guys. I did read Hogenauer's paper. My question is, he mentioned Bmax is the upper and also the low bound of bitwidth required for every single integrator and differentiator, without proof. This is found in the two paragraphs under equation 11. Modulo operation is...
hogenauer pruning
Hi all,
I need to implement a CIC decimator in an FPGA in fixed-point format. Everything works fine in floating point format in Matlab simulations. I am now translating the design from floating point to fixed point, and have to design the bit width of each integrator and...
Hi All,
I am a bit scared after reading Abidi's papers on SDR. Sounds like more and more stuffs are done in digital domain, the analog portion will get less and less important, utimately be removed. The shrinking of device size simply go against analog circuit's linearity, noise....etc. Look...
Hi All,
I am trying to understand the constant-gm circuit more. Please refer to the enclosed screen capture. How come Iout is not constant with with VDS sweeps from 1 to 3V?
Thanks,
Mesfet+
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
