Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by MelonPie

  1. M

    What interfaces are suitable for CESoP and SAToP?

    Hello, Is there anyone know what interfaces are suitable to CESoP and SAToP? Thanks! MelonPie
  2. M

    SPI-4.2 (preconfigured bounded interval)

    Hello, I read the SPI-4.2 specification and found a phrase that I don`t understand. Does anybody understand the meaning of "preconfigured bounded interval"? Thanks in advance.
  3. M

    chip to chip connection with Ethernet

    dainis, Thank you very much!
  4. M

    chip to chip connection with Ethernet

    Hello dainis, Thanks for your reply. Can you tell me what IP can be implemented into a FPGA as PHY mode? Since I am using Xilinx`s FPGA which doesn`t support SMII. I would like to use SGMII and run at 100Mbps only to connect from FPGA A to FPGA B. Best Regards, MelonPie
  5. M

    chip to chip connection with Ethernet

    Hello, I am thinking of using Gigabit Ethernet to have chip to chip interconnection. How can I achieve this? Can I connnect Chip A to Chip B by SGMII without physical layer in between? Chip A (GEMAC) -------> Chip B (GEMAC) ______________SGMII_______________ Thanks!

Part and Inventory Search

Back
Top