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Recent content by mehrara

  1. M

    ERROR:Place:120 - There were not enough sites to place ...

    error:place:120 hi I am trying to implement a Viterbi decoder on a Xilinx V-II (XC2V1000-4) but during the placement after warnings of the following type: WARNING:Place:119 - Unable to find location. TBUF component up0_I12_8 not placed. TBUF "up0_I12_8". the placer halts with the...
  2. M

    Special symbol to indicate the start of a binary packet?

    Well! If I have understood correctlly 47H symbol may solve your problem as it is the start of frame marker in DVB standard!!!
  3. M

    Serialing CObArrays in VC++

    Hi I have declared a CObArray in the document of a SDI program. this array contains object which have another cobarray for themselves. Parent of both of these objecs is CButton class. When I want to Serialize the objects I call the first CObArray Serialize in the Serialize of the Document class...
  4. M

    How to disable USB bandwidth limitation ?

    USB bandwidth limitation hi I want to interface my hardware design to pc through usb and I need nearly the full bandwidth of USB 2.0 but in best situation I have only 48 Mb/s. I found something in my usb host controller properties in device manager. It reserves only 10% of bandwidth for the...
  5. M

    Parrallel simulation using modelsim...

    Hi Does anyone know if I can simulate my VHDL design in modelsim by using 2 or more PCs to gain a higher simulation speed? (I guess we can do that in Matlab)
  6. M

    How to use IBIS model in a VHDL Project?

    I want to build up a high speed connection between FPGA and computer. I chose USB and I want to use Cypress`s CY68013 USB transciver. In order to test my design I want to do Post place and route simulation in ModelSim. What can I do? Thanks p.s. I think the functionality of the IC is too...
  7. M

    How to use IBIS model in a VHDL Project?

    hi I have a vhdl project in ISE. I use Cypress's CY68013 USB transciver and the only model available for it in cypress.com is IBIS. How can I simulate my design ?(in modelsim) Thanks...
  8. M

    How do I use Block RAM in my spartanII based design?

    hi I created the same core(I mean single block memory) and after those commented lines ! it contains the following port definition: LIBRARY ieee; USE ieee.std_logic_1164.ALL; Library XilinxCoreLib; ENTITY test IS port ( addr: IN std_logic_VECTOR(7 downto 0); clk: IN std_logic; din: IN...
  9. M

    Xilinx Impact gives error when FPGA is configured Via JTAG

    hi the problem was due to my cable. I used an old cable and it worked correctlly. but I don`t know why I can not program Spartan II with a cable by which I have programmed Virtex-E!
  10. M

    Avnet Virtex II pro Evaluation Kit

    hi I want to implement my design in Avnet Virtex II pro Evaluation kit but before buyng it I prefer to make sure that the design fits in the FPGA located on it.so I need the schematic of the board.or pin assignment of the FPGA. can anyone help me? thanks
  11. M

    How do I use Block RAM in my spartanII based design?

    hi when you want to use the ram component that you `ve generated with CoreGen you can find the component port definitiion in the vhd file that coregen has created. I have used Dual Port Ram from coregen several times and I had no problem.
  12. M

    Problem with updating Xilinx to ver. 5.2

    hi Don`t you have VHDL XST synthesis tool in project properties window? besides you can install leonardo spectrum 2001. and use in in ISE.
  13. M

    Xilinx Impact gives error when FPGA is configured Via JTAG

    bit file impact hi I use ISE 5.1i for both synthesis and downloading the bit stream.( I also installed the service pack but the problem persisted) and I use XST for synthesising.did you mean that I should download the new bsd files from Xilinx? p.s: I used the same software for cofiguring the...
  14. M

    Xilinx Impact gives error when FPGA is configured Via JTAG

    impact bsdl error hi I have the same problem with xilinx saprtan II (xc2s150). I connect the cable directly to boundary scan pins in the device through a test board. should I pull-up or pull-down any of these pins? if not what may be the source of problem in my hardware I had configured a...
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