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I am using hpe 560 SFP plus adapter from intel in one side. I have an ultra scale FPGA from kintex family in the other side. I create 8K jumbo Ethernet packets in FPGA. i used winpacp and visual studio in windows. i have packet loss. Is there any idea how to capture this data rate in windows?
hi i have a virtex 4 and 16p prom on my board. i can program fpga seperately. and i can program prom too. but prom cant load fpga. i used master slave serial mode.
im sure about the code and the schematics. how can i test done pin and cclk_0 of fpga in bank0?
well, my clock frequency is 10 mhz. and chip scope clock is 320mhz.
i used a dcm which its input is lclk and output 4xlclk=320mhz
i think its true. pll is not locked. but what the reason?
input clock?
tanx
so whats your idea about the higher frequency that i can not see any clock(lclk or ADclk)in spectrum?
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i used a 240 mhz clock from dcm as chipscope clock. but the dcm input a 100mhz clock from mother board
i designed a daughter board. it has an fmc connector, cdce62005 and ads5263. i have several problems. i listed my problems. before that i want to give a summary about what i did.
summary: i used a single 10 mhz clock as an input for cdce62005. cdce62005 programed to pass this signal to its lvds...
hi all,
I want to make the pcb of a schematic in ALTUM. i have an ADC in my schematic. outputs of ADC are differential signals. i want to use polygan between every differential output. fore example between o1n,o1p and o2n,o2p. i dont have any idea about the distance of polygan and each of...
Hi all
i have an eight layer board. i used 1 cdce as clock. by the way i used 2 ADCs too. the impedance of my lVDS signals is 100(ohm). i have some single ended signals like SPI_MISO, SPI_MOSI,.. . what is the typical impedance of these traces?
help me
tanx
hi i want to plot the IDDQ of a simple design. i have two ways help me to choose one. hear are the ways
1. make a layout using soc encounter and convert it to spice model using calibre
2. synthesize the design using design compiler and using command v2s to extract the spice model
help me plz
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