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Add on point, Trial route does not fix DRC's. (Takes less time)
Trial Route will give idea on routing congestion at early stage so that one can avoid iterations and save timing. This takes very less time than Global routing and Detail routing. Detail routing will take time to fix DRC's.
This...
max_transition
Hi Friends,
As i know the max cap and max trans values are taken from the lib's.
If in case we have DRV violations and want to force my max cap and max trans values how can we deside the values.
Example: set_max_capacitance 2 (for Design)
Re: Max & Min delays
Then what about
worst_max.lib
worst_min.lib
worst_max.db
worst_min.db
simillarly
best_max.lib
best_min.lib
best_max.db
best_min.db please can you explain
derate ocv
Thank you Arjun i am clear now.
I am trying to understand weather it is only based in OCV derating or any other factors involved while library characterization.
max&min
Thank you for infrmation
I would like to make clear on min & max corners.
Max corner: PVT- Slow Low High
Min corner: PVT-Fast High Low
Now :- Please correct me if iam wrong
Max corner:
setup: PVT- Slow Low High
Hold: PVT- Slow High Low or Fast High Low
Min corner:
setup: PVT-...
irdrop
Hi All,
Below are the methods i know to reduce IR drop
1. Adding more stripes
2. Spread the logic (if hotspots are at congested areas)
3. Using low power cells
4. Adding proper vias
5. Clock gating
6. Proper CTS structure (Minimising clock buffers in clock tree as they switch very...
maxmin vs minmax
Hi Dear all,
While STA we close timing in max and min corners
max min
setup hold setup hold
setup (maxmax maxmin)
hold(minmin minmax)
what is min delay in max corner?
what is max delay in min corner?
why lower metal has his resistance
Hi All.
Why only top metl layer should be low resistance why not bottm Layers.
I mean viseversa.
Please correct me if iam wrong.
Reason1.Top metal layers width is more than the lower metal layers (R=row*L/A)
if so why should?
Reason2.Top metal layer are...
Thank you, I answered the same as you mentioned in an interview.
But they asked counter question how can you prove.
Thanks lot for giving good explaination.
Hi,
Please can any one explain me with derivations (formulas) How adding buffers in a long Path (net) will reduce the delays?
A <------------------------->B (path having 500ps)
now adding buffer in the path (Fanout of A is one, no problem with fanout)
A<--------|>----------->B (path delay...
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