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Thanks for the tip on the opposite edge for rtl, we'll try it.
for the std lib, we've add some #delay to the flop cells, and it works on the pure netlist sim with +delay_mode_unit option
Sorry I wasn't describe the situation clearly enough.
1. we're just trying the pre-sim with no_timing_check and no_specify options, so the simulator won't check setup/hold violations
2. I have lost the wave and logic with the race condition. do you mean we have to manually add fake delays in the...
How to avoid race condition on RTL and Netlist mixed simulation
Hi,
Currently we have met some race conditions when doing RTL + Netlist simulation using irun, where RTL is the top module and some blocks are Netlist.
We tried +delay_mode_unit and +delay_mode_zero option, and still fails...
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